The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 26, 2025
Filed:
Jan. 10, 2022
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Shang-Wen Chang, Hsinchu County, TW;
Yi-Hsiung Lin, Hsinchu County, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;
Abstract
A method and structure for forming a local interconnect, without routing the local interconnect through an overlying metal layer. In various embodiments, a first dielectric layer is formed over a gate stack of at least one device and a second dielectric layer is formed over a contact metal layer of the at least one device. In various embodiments, a selective etching process is performed to remove the second dielectric layer and expose the contact metal layer, without substantial removal of the first dielectric layer. In some examples, a metal VIA layer is deposited over the at least one device. The metal VIA layer contacts the contact metal layer and provides a local interconnect structure. In some embodiments, a multi-level interconnect network overlying the local interconnect structure is formed.