The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 26, 2025

Filed:

Dec. 21, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Veronica Strong, Hillsboro, OR (US);

Robert Jordan, Portland, OR (US);

Telesphor Kamgaing, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/15 (2006.01); H01L 23/498 (2006.01); H01G 4/012 (2006.01); H01G 4/224 (2006.01); H01G 4/33 (2006.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); H01L 23/15 (2013.01); H01L 23/49816 (2013.01); H01L 23/49827 (2013.01); H01G 4/012 (2013.01); H01G 4/224 (2013.01); H01G 4/33 (2013.01);
Abstract

Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a substrate with a first surface and a second surface, where the substrate comprises glass. In an embodiment, the electronic package further comprises a via opening through the substrate, where sidewalls of the via opening have a root mean squared (RMS) surface roughness that is approximately 100 nm or greater. In an embodiment, the electronic package further comprises a liner over the sidewalls of the via opening, where an RMS surface roughness of the liner is approximately 50 nm or smaller. An electronic package may further comprise a via through the via opening.


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