The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 19, 2025

Filed:

Aug. 02, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Ting-Yeh Chen, Hsinchu, TW;

Wei-Yang Lee, Taipei, TW;

Chia-Pin Lin, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 62/10 (2025.01); H01L 21/28 (2025.01); H10D 64/01 (2025.01);
U.S. Cl.
CPC ...
H10D 62/115 (2025.01); H01L 21/28194 (2013.01); H10D 64/017 (2025.01); H10D 64/021 (2025.01);
Abstract

A method includes providing a structure having a substrate, fins and an isolation structure over the substrate, wherein each fin includes first and second semiconductor layers alternatingly stacked. The method further includes depositing a first dielectric layer over top and sidewalls of the fins and over a top surface of the isolation structure; depositing a second dielectric layer over the first dielectric layer; and etching back the first and the second dielectric layers such that they remain on the top surface of the isolation structure and are removed from the top and sidewalls of the fins. The method further includes forming dummy gate stacks, gate spacers, source and drain trenches, and inner spacers, wherein the first and the second dielectric layers remain on the top surface of the isolation structure.


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