The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 19, 2025
Filed:
Sep. 22, 2020
Applicant:
Texas Instruments Incorporated, Dallas, TX (US);
Inventors:
Jie Chen, Plano, TX (US);
Yong Xie, Plano, TX (US);
Rajen Manicon Murugan, Dallas, TX (US);
Woochan Kim, San Jose, CA (US);
Assignee:
TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/66 (2006.01); H01L 25/16 (2023.01);
U.S. Cl.
CPC ...
H01L 24/24 (2013.01); H01L 24/73 (2013.01); H01L 24/82 (2013.01); H01L 24/92 (2013.01); H01L 25/16 (2013.01); H01L 23/66 (2013.01); H01L 2223/6666 (2013.01); H01L 2224/24101 (2013.01); H01L 2224/24175 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/82102 (2013.01); H01L 2224/82104 (2013.01); H01L 2224/92244 (2013.01); H01L 2924/1033 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/1426 (2013.01);
Abstract
In described examples of a circuit module, a multilayer substrate has a conductive pad formed on a surface of the multilayer substrate. An integrated circuit (IC) die is bonded to the surface of the substrate in dead bug manner, such that a set of bond pads formed on a surface of the IC die are exposed. A planar interconnect line formed by printed ink couples the set of bond pads to the conductive pad.