The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 19, 2025

Filed:

Jan. 02, 2024
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Min-Hsiu Hung, Tainan, TW;

Chien Chang, Hsinchu, TW;

Yi-Hsiang Chao, New Taipei, TW;

Hung-Yi Huang, Hsinchu, TW;

Chih-Wei Chang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/285 (2006.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 64/01 (2025.01);
U.S. Cl.
CPC ...
H01L 21/28518 (2013.01); H01L 21/02274 (2013.01); H01L 21/28556 (2013.01); H01L 21/76802 (2013.01); H01L 21/76879 (2013.01); H10D 30/024 (2025.01); H10D 30/62 (2025.01); H10D 64/017 (2025.01);
Abstract

A method of forming a semiconductor device includes forming source/drain regions on opposing sides of a gate structure, where the gate structure is over a fin and surrounded by a first dielectric layer; forming openings in the first dielectric layer to expose the source/drain regions; selectively forming silicide regions in the openings on the source/drain regions using a plasma-enhanced chemical vapor deposition (PECVD) process; and filling the openings with an electrically conductive material.


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