The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 12, 2025

Filed:

May. 13, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Wan-Hsien Lin, Hsinchu, TW;

Ting-Gang Chen, Taipei, TW;

Chin-Wei Lin, Taoyuan, TW;

Chi On Chui, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/535 (2006.01); H01L 21/768 (2006.01); H01L 23/532 (2006.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01);
U.S. Cl.
CPC ...
H01L 23/535 (2013.01); H01L 21/76805 (2013.01); H01L 21/76831 (2013.01); H01L 21/76895 (2013.01); H01L 23/53242 (2013.01); H01L 23/53257 (2013.01); H10D 30/024 (2025.01); H10D 30/6211 (2025.01);
Abstract

Methods for selectively depositing a metal layer over a gate structure and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a channel region over a semiconductor substrate; a gate structure over the channel region; a gate spacer adjacent the gate structure; a first dielectric layer adjacent the gate spacer; a barrier layer contacting a top surface of the gate spacer and a side surface of the first dielectric layer, the barrier layer including a nitride; and a metal layer over the gate structure adjacent the barrier layer, the metal layer having a first width equal to a second width of the gate structure.


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