The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 05, 2025
Filed:
Jun. 15, 2021
Intel Corporation, Santa Clara, CA (US);
Leonard P. Guler, Hillsboro, OR (US);
Chanaka Munasinghe, Portland, OR (US);
Makram Abd El Qader, Hillsboro, OR (US);
Marie Conte, Hillsboro, OR (US);
Saurabh Morarka, Hillsboro, OR (US);
Elliot N. Tan, Portland, OR (US);
Krishna Ganesan, Portland, OR (US);
Mohit K. Haran, Hillsboro, OR (US);
Charles H. Wallace, Portland, OR (US);
Tahir Ghani, Portland, OR (US);
Sean Pursel, Hillsboro, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
An integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. A first dielectric gate spacer is laterally around the first gate stack and has a portion along an end of the first gate stack and in the gap. A second dielectric gate spacer is laterally around the second gate stack and has a portion along an end of the second gate stack and in the gap. The portion of the second dielectric gate spacer is laterally merged with the portion of the first dielectric gate spacer in the gap.