The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 05, 2025

Filed:

Apr. 24, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Ya-Yi Tsai, Hsinchu, TW;

Chi-Hsiang Chang, Hsinchu, TW;

Shih-Yao Lin, New Taipei, TW;

Tzu-Chung Wang, Hsinchu, TW;

Shu-Yuan Ku, Zhubei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/62 (2025.01); H10D 30/01 (2025.01); H10D 62/10 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H10D 30/0243 (2025.01); H10D 30/62 (2025.01); H10D 30/6219 (2025.01); H10D 62/115 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01);
Abstract

A semiconductor device and method of fabricating a semiconductor device involves formation of a trench above a fin (e.g. a fin of a FinFET device) of the semiconductor device and formation of a multi-layer dielectric structure within the trench. The profile of the multi-layer dielectric structure can be controlled depending on the application to reduce shadowing effects and reduce cut failure risk, among other possible benefits. The multi-layer dielectric structure can include two layers, three layers, or any number of layers and can have a stepped profile, a linear profile, or any other type of profile.


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