The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 05, 2025

Filed:

Sep. 07, 2023
Applicant:

Adeia Semiconductor Bonding Technologies Inc., San Jose, CA (US);

Inventors:

Rajesh Katkar, San Jose, CA (US);

Liang Wang, Milpitas, CA (US);

Cyprian Emeka Uzoh, San Jose, CA (US);

Shaowu Huang, Sunnyvale, CA (US);

Guilian Gao, San Jose, CA (US);

Ilyas Mohammed, Santa Clara, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/04 (2006.01); B81B 7/00 (2006.01); B81C 1/00 (2006.01); H01L 23/02 (2006.01); H01L 23/053 (2006.01); H01L 23/10 (2006.01);
U.S. Cl.
CPC ...
H01L 23/10 (2013.01); B81B 7/0032 (2013.01); B81B 7/0074 (2013.01); B81C 1/00261 (2013.01); B81C 1/00269 (2013.01); B81C 1/00333 (2013.01); H01L 23/02 (2013.01); H01L 23/04 (2013.01); H01L 23/053 (2013.01); B81C 2203/038 (2013.01);
Abstract

Representative implementations of techniques and devices provide seals for sealing the joints of bonded microelectronic devices as well as bonded and sealed microelectronic assemblies. Seals are disposed at joined surfaces of stacked dies and wafers to seal the joined surfaces. The seals may be disposed at an exterior periphery of the bonded microelectronic devices or disposed within the periphery using the various techniques.


Find Patent Forward Citations

Loading…