The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 29, 2025

Filed:

Nov. 02, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Jeffrey S. Mcneil, Nampa, ID (US);

Eric N. Lee, San Jose, CA (US);

Vamsi Pavan Rayaprolu, Santa Clara, CA (US);

Sivagnanam Parthasarathy, Carlsbad, CA (US);

Kishore Kumar Muchherla, San Jose, CA (US);

Patrick R. Khayat, San Diego, CA (US);

Violante Moschiano, Avezzano, IT;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0613 (2013.01); G06F 3/0653 (2013.01); G06F 3/0679 (2013.01);
Abstract

Described are systems and methods for validating read level voltage in memory devices. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines; and a controller coupled to the memory array, the controller to perform operations comprising: causing a read level voltage to be applied to a specified wordline of the plurality of wordlines; receiving an actual bit count reflecting a number of memory cells that have their respective threshold voltages below the read level voltage; and responsive to determining that a difference of an expected bit count and the actual bit count exceeds a predetermined threshold value, adjusting the read level voltage.


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