The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 22, 2025

Filed:

Jan. 24, 2023
Applicant:

Stmicroelectronics International N.v., Geneva, CH;

Inventors:

Venkata Narayanan Srinivasan, Greater Noida, IN;

Umesh Chandra Srivastava, Greater Noida, IN;

Shiv Kumar Vats, Greater Noida, IN;

Manish Sharma, Gurgaon, IN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/3185 (2006.01); G01R 31/3187 (2006.01);
U.S. Cl.
CPC ...
G01R 31/318544 (2013.01); G01R 31/318536 (2013.01); G01R 31/318541 (2013.01); G01R 31/318597 (2013.01); G01R 31/3187 (2013.01);
Abstract

According to an embodiment, a digital circuit includes an OR gate and a flip-flop. The OR gate includes a first input and a second input. The first input of the OR gate is coupled to a control signal, and the second input of the OR gate is coupled to an uncovered functional combination logic of the digital circuit. The first input of the OR gate is configured to be pulled low by the control signal in response to setting the digital circuit in a configuration to test the uncovered functional combination logic. The flip-flop includes a reset pin or a set pin coupled to the output of the OR gate. The output of the flip-flop is configured to be observed during a testing of the uncovered functional combination logic to detect defects in the digital circuit.


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