The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 15, 2025

Filed:

May. 20, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Seng Kim Ye, Singapore, SG;

Kelvin Tan Aik Boo, Singapore, SG;

Hong Wan Ng, Singapore, SG;

Chin Hui Chong, Singapore, SG;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0652 (2013.01); H01L 24/48 (2013.01); H01L 24/49 (2013.01); H01L 25/50 (2013.01); H01L 2224/48011 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48147 (2013.01); H01L 2224/48221 (2013.01); H01L 2224/4903 (2013.01); H01L 2224/49052 (2013.01); H01L 2224/49177 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06527 (2013.01); H01L 2225/06562 (2013.01);
Abstract

A semiconductor package having a package substrate including an upper surface, a controller, a first die stack, and a second die stack. The controller, the first die stack, and the second die stack are at the upper surface. The first die stack includes a first shingled sub-stack and a first reverse-shingled sub-stack. The first die stack also includes a first bridging chip between the first shingled and reverse-shingled sub-stacks. The second die stack similarly includes a second shingled sub-stack and a second reverse-shingled sub-stack. The second die stack also includes a second bridging chip bonded to the top of the second reverse-shingled sub-stack. At least a portion of a bottom semiconductor die of the first reverse-shingled sub-stack is vertically aligned with a semiconductor die of the second shingled sub-stack and a semiconductor die of the second reverse-shingled sub-stack.


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