The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 15, 2025
Filed:
Feb. 23, 2022
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Kris Lipu Chuang, Hsinchu, TW;
Tzu-Sung Huang, Tainan, TW;
Chih-Wei Lin, Hsinchu County, TW;
Yu-fu Chen, Hsinchu, TW;
Hsin-Yu Pan, Taipei, TW;
Hao-Yi Tsai, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Abstract
A package structure includes a first redistribution layer, a semiconductor die, and through vias. The first redistribution layer includes dielectric layers, first conductive patterns, and second conductive patterns. The dielectric layers are located in a core region and a peripheral region of the first redistribution layer. The first conductive patterns are embedded in the dielectric layers in the core region, wherein the first conductive patterns are arranged in the core region with a pattern density that gradually increases or decreases from a center of the core region to a boundary of the core region. The second conductive patterns are embedded in the dielectric layers in the peripheral region. The semiconductor die is disposed on the core region over the first conductive patterns. The through vias are disposed on the peripheral region and electrically connected to the second conductive patterns.