The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 15, 2025

Filed:

Jul. 22, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;

Inventors:

Yu-Sheng Lin, Zhubei, TW;

Hsin-Hsien Lee, Taoyuan County, TW;

Jyun-Lin Wu, Hsinchu, TW;

Yao-Chun Chuang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/13 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/13 (2013.01); H01L 21/4853 (2013.01); H01L 21/486 (2013.01); H01L 21/563 (2013.01); H01L 23/3185 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01);
Abstract

A semiconductor structure includes an interposer having a first planar surface, a set of non-horizontal surfaces having a top periphery that are adjoined to a periphery of the first planar surface, and a frame-shaped surface adjoined to a bottom periphery of the set of non-horizontal surfaces, sidewalls adjoined to the frame-shaped surface, and a second planar surface adjoined to the sidewalls; at least one semiconductor die attached to the interposer through a respective array of solder material portions; and an underfill material portion located between the interposer and the at least one semiconductor die and contacting a portion of the first planar surface.


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