The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 15, 2025

Filed:

May. 17, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Hsiu-Wen Hsueh, Taichung, TW;

Chii-Ping Chen, Hsinchu, TW;

Po-Hsiang Huang, Taipei, TW;

Ya-Ching Tseng, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/535 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76844 (2013.01); H01L 21/76805 (2013.01); H01L 21/76834 (2013.01); H01L 21/7684 (2013.01); H01L 21/76846 (2013.01); H01L 21/76849 (2013.01); H01L 21/76895 (2013.01); H01L 23/535 (2013.01);
Abstract

The present disclosure relates a method of forming an integrated chip. The method includes forming a first interconnect within a first inter-level dielectric (ILD) layer over a substrate, and forming a second ILD layer over the first ILD layer. The second ILD layer is patterned to form an interconnect opening that exposes the first interconnect. A blocking layer is formed onto the first interconnect. A barrier layer is formed within the interconnect opening and the blocking layer is removed to expose the first interconnect. A second interconnect is formed within the interconnect opening.


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