The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 15, 2025
Filed:
May. 17, 2021
Intel Ndtm Us Llc, Santa Clara, CA (US);
Rifat Ferdous, Lafayette, IN (US);
Sung-Taeg Kang, Palo Alto, CA (US);
Rohit S. Shenoy, Fremont, CA (US);
Ali Khakifirooz, Brookline, MA (US);
Dipanjan Basu, Portland, OR (US);
Intel NDTM US LLC, Santa Clara, CA (US);
Abstract
At the end of or after a reading operation in a 3D (three dimensional) NAND array, the wordlines of the 3D NAND array can be transitioned to ground in a staggered manner. The 3D NAND array includes a 3D stack with multiple wordlines vertically stacked, including a bottom-most wordline, a top-most wordline, and middle wordlines between the bottom-most wordline and the top-most wordline. A controller that controls the reading can set the multiple wordlines to a high voltage at the end or after the reading operation and then transition a selected wordline of the multiple wordlines from the high voltage to ground prior to transitioning the other wordlines to ground. Thus, the controller will transition the other wordlines from the high voltage to ground after a delay.