The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 01, 2025

Filed:

Sep. 24, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Kirby Maxey, Hillsboro, OR (US);

Ashish Verma Penumatcha, Beaverton, OR (US);

Carl Naylor, Portland, OR (US);

Chelsey Dorow, Portland, OR (US);

Kevin O'Brien, Portland, OR (US);

Shriram Shivaraman, Hillsboro, OR (US);

Tanay Gosavi, Portland, OR (US);

Uygar Avci, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 64/23 (2025.01); H10D 62/80 (2025.01); H10D 64/01 (2025.01); H10D 64/27 (2025.01); H10D 84/83 (2025.01);
U.S. Cl.
CPC ...
H10D 64/258 (2025.01); H10D 62/80 (2025.01); H10D 64/01 (2025.01); H10D 64/513 (2025.01); H10D 84/83 (2025.01);
Abstract

Transistors, devices, systems, and methods are discussed related to transistors including a number of 2D material channel layers and source and drain control electrodes coupled to source and drain control regions of the 2D material channels. The source and drain control electrodes are on opposite sides of a gate electrode, which controls a channel region of the 2D material channels. The source and drain control electrodes provide for reduced contact resistance of the transistor, the ability to create complex logic gates, and other advantages.


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