The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 01, 2025

Filed:

Jan. 29, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Jen-Hong Chang, Hsinchu, TW;

Yuan-Ching Peng, Hsinchu, TW;

Chung-Ting Ko, Kaohsiung, TW;

Kuo-Yi Chao, Hsinchu, TW;

Chia-Cheng Chao, Hsinchu, TW;

You-Ting Lin, Miaoli County, TW;

Chih-Chung Chang, Nantou County, TW;

Yi-Hsiu Liu, Hsinchu, TW;

Jiun-Ming Kuo, Hsinchu, TW;

Sung-En Lin, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/94 (2006.01); H01L 29/76 (2006.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 62/10 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10D 62/115 (2025.01); H10D 84/0151 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01);
Abstract

Semiconductor structures and methods of forming the same are provided. A method according to the present disclosure includes forming a stack of epitaxial layers over a substrate, forming a first fin-like structure and a second fin-like structure from the stack, forming an isolation feature between the first fin-like structure and the second fin-like structure, forming a cladding layer over the first fin-like structure and the second fin-like structure, conformally depositing a first dielectric layer over the cladding layer, depositing a second dielectric layer over the first dielectric layer, planarizing the first dielectric layer and the second dielectric layer until the cladding layer are exposed, performing an etch process to etch the second dielectric layer to form a helmet recess, performing a trimming process to trim the first dielectric layer to widen the helmet recess, and depositing a helmet feature in the widened helmet recess.


Find Patent Forward Citations

Loading…