The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 01, 2025

Filed:

Dec. 08, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Chun-Chieh Lu, Taipei, TW;

Sai-Hooi Yeong, Zhubei, TW;

Yu-Ming Lin, Hsinchu, TW;

Mauricio Manfrini, Zhubei, TW;

Georgios Vellianitis, Heverlee, BE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 51/20 (2023.01); H10B 51/00 (2023.01); H10B 51/10 (2023.01); H10B 51/30 (2023.01); H10D 30/01 (2025.01); H10D 64/68 (2025.01);
U.S. Cl.
CPC ...
H10B 51/20 (2023.02); H10B 51/00 (2023.02); H10B 51/10 (2023.02); H10B 51/30 (2023.02); H10D 30/0415 (2025.01); H10D 64/689 (2025.01);
Abstract

A ferroelectric memory device includes a multi-layer stack, a channel layer and a III-V based ferroelectric layer. The multi-layer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers of the multi-layer stack. The III-V based ferroelectric layer is disposed between the channel layer and the multi-layer stack, and includes at least one element selected from Group III elements, at least one element selected from Group V elements, and at least one element selected from transition metal elements.


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