The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 24, 2025

Filed:

Sep. 23, 2022
Applicant:

Changxin Memory Technologies, Inc., Hefei, CN;

Inventors:

Guangsu Shao, Hefei, CN;

Deyuan Xiao, Hefei, CN;

Yunsong Qiu, Hefei, CN;

Yi Jiang, Hefei, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 12/00 (2023.01);
U.S. Cl.
CPC ...
H10B 12/482 (2023.02); H10B 12/02 (2023.02);
Abstract

Embodiments relate to a method for fabricating a semiconductor structure. The method includes: providing a substrate, where pillars arranged in an array are formed on a surface of the substrate, and bit lines extending along a first direction are formed at bottoms of the pillars; forming, between adjacent two of the pillars, a first groove extending along a second direction; forming an isolation layer on the substrate, where the isolation layer is filled in the first groove and is filled between adjacent two of the bit lines; etching the isolation layer to expose a surface of the pillar, where a first sub isolation layer positioned in the first groove is lower than a second sub isolation layer; forming a word line surrounding a side wall of the pillar, where a surface of the word line is not higher than a surface of the second sub isolation layer; and forming a dielectric layer on the word line.


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