The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 24, 2025

Filed:

Jun. 13, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Biancun Xie, Chandler, AZ (US);

Jianyong Xie, Chandler, AZ (US);

Sujit Sharan, Chandler, AZ (US);

Debendra Mallik, Chandler, AZ (US);

Robert L. Sankman, Phoenix, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01); H01L 23/498 (2006.01); H01L 23/64 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0655 (2013.01); H01L 23/5383 (2013.01); H01L 23/5384 (2013.01); H01L 23/5385 (2013.01); H01L 23/5386 (2013.01); H01L 24/16 (2013.01); H01L 23/49816 (2013.01); H01L 23/642 (2013.01); H01L 2224/16227 (2013.01);
Abstract

Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly including a substrate having a conductive plane; and a bridge having first contacts at a first surface and second contacts at an opposing second surface, wherein the bridge is embedded in the substrate and coupled to the conductive plane in the substrate via the first contacts, wherein the bridge is coupled to a first die and a second die via the second contacts, and wherein the bridge does not include a silicon substrate.


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