The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 24, 2025

Filed:

Dec. 07, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Eng Huat Goh, Ayer Itam, MY;

Kyle Davidson, Hillsboro, OR (US);

Min Suet Lim, Penang, MY;

Kevin Byrd, Portland, OR (US);

James Wade, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/13 (2006.01); H01L 23/498 (2006.01); H01L 23/52 (2006.01); H01L 23/64 (2006.01);
U.S. Cl.
CPC ...
H01L 24/32 (2013.01); H01L 21/563 (2013.01); H01L 23/13 (2013.01); H01L 23/49833 (2013.01); H01L 23/642 (2013.01); H01L 24/16 (2013.01); H01L 24/17 (2013.01); H01L 24/73 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/17135 (2013.01); H01L 2224/32237 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/9202 (2013.01); H01L 2224/92125 (2013.01); H01L 2924/19106 (2013.01);
Abstract

An integrated circuit package may be fabricated by disposing an underfill material between an electronic substrate and an integrated circuit device through an opening in the electronic substrate. In one embodiment, an integrated circuit assembly may include an electronic substrate having a first surface and an opposing second surface, wherein the electronic substrate includes at least one opening extending from the first surface to the second surface. The integrated circuit assembly may further include an integrated circuit device, wherein the integrated circuit device is electrically attached to the electronic substrate with at least one interconnect, and an underfill material may be disposed between the first surface of the electronic substrate and the integrated circuit device, wherein a portion of the underfill material extends into the opening in the electronic substrate.


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