The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 24, 2025

Filed:

Mar. 21, 2024
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Shrenik Kothari, Phoenix, AZ (US);

Chandra Mohan Jha, Tempe, AZ (US);

Weihua Tang, Chandler, AZ (US);

Robert Sankman, Phoenix, AZ (US);

Xavier Brun, Chandler, AZ (US);

Pooya Tadayon, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/42 (2006.01); H01L 23/367 (2006.01); H01L 23/373 (2006.01); H01L 23/522 (2006.01); H01L 23/00 (2006.01); H01L 23/13 (2006.01); H01L 23/495 (2006.01); H01L 23/538 (2006.01); H01L 25/07 (2006.01); H01L 25/18 (2023.01);
U.S. Cl.
CPC ...
H01L 23/42 (2013.01); H01L 23/367 (2013.01); H01L 23/3738 (2013.01); H01L 23/522 (2013.01); H01L 23/13 (2013.01); H01L 23/49575 (2013.01); H01L 23/5384 (2013.01); H01L 24/20 (2013.01); H01L 25/072 (2013.01); H01L 25/18 (2013.01);
Abstract

Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.


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