The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 24, 2025

Filed:

May. 13, 2022
Applicant:

Changxin Memory Technologies, Inc., Hefei, CN;

Inventors:

Longyang Chen, Hefei, CN;

Shijie Bai, Hefei, CN;

Zhongming Liu, Hefei, CN;

Yexiao Yu, Hefei, CN;

Xianguo Zhou, Hefei, CN;

Bin Zhao, Hefei, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/033 (2006.01); H01L 21/027 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01); H10B 12/00 (2023.01);
U.S. Cl.
CPC ...
H01L 21/0337 (2013.01); H01L 21/0276 (2013.01); H01L 21/0332 (2013.01); H01L 21/31116 (2013.01); H01L 21/31122 (2013.01); H01L 21/32135 (2013.01); H01L 21/32139 (2013.01); H10B 12/01 (2023.02);
Abstract

A preparation method for a semiconductor structure and a semiconductor structure are provided. Herein, the preparation method comprises: providing a structure to be processed, wherein the structure to be processed comprises a substrate, and an etching target layer, a bottom mask layer and a first mask layer stacked on the substrate; patterning the first mask layer to form a first pattern, the first pattern exposing parts of the bottom mask layer; forming spacers with vertical sidewall morphology on sidewalls of the first mask layer; removing the first mask layer; filling a gap between the spacers with a filling layer, in which a material of the spacers to a material of the filling layer has a high etching selectivity ratio; and removing the spacers.


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