The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 17, 2025
Filed:
Jul. 29, 2021
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Inventors:
Assignee:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01J 37/32 (2006.01); C23C 16/455 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01J 37/32816 (2013.01); C23C 16/45542 (2013.01); H01J 37/32119 (2013.01); H01J 37/32449 (2013.01); H01J 37/32715 (2013.01); H01L 21/02274 (2013.01); H01L 21/02277 (2013.01); H01L 21/0228 (2013.01); H01J 2237/1825 (2013.01); H01J 2237/2007 (2013.01); H01J 2237/332 (2013.01);
Abstract
A method of depositing a layer on a semiconductor workpiece is disclosed. The method includes placing the semiconductor workpiece on a wafer chuck in a processing chamber, introducing a first precursor into the processing chamber, introducing a second precursor into the processing chamber, and while the second precursor is in the processing chamber, applying radiation to the semiconductor workpiece, whereby a surface of the semiconductor workpiece is heated. The method also includes, while the second precursor is in the processing chamber, applying a voltage bias to the wafer chuck.