The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 10, 2025

Filed:

Jun. 24, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Rui Ma, Portland, OR (US);

Kalyan Kolluru, Portland, OR (US);

Nicholas Thomson, Hillsboro, OR (US);

Ayan Kar, Portland, OR (US);

Benjamin Orr, Portland, OR (US);

Nathan Jack, Forest Grove, OR (US);

Biswajeet Guha, Hillsboro, OR (US);

Brian Greene, Portland, OR (US);

Chung-Hsun Lin, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 89/60 (2025.01); H10D 18/00 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 62/17 (2025.01); H10D 62/822 (2025.01); H10D 64/27 (2025.01); H10D 84/40 (2025.01);
U.S. Cl.
CPC ...
H10D 89/713 (2025.01);
Abstract

Substrate-less silicon controlled rectifier (SCR) integrated circuit structures, and methods of fabricating substrate-less silicon controlled rectifier (SCR) integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a first fin portion and a second fin portion that meet at a junction. A plurality of gate structures is over the first fin portion and a second fin portion. A plurality of P-type epitaxial structures and N-type epitaxial structures is between corresponding adjacent ones of the plurality of gate structures. Pairs of the P-type epitaxial structures alternate with pairs of the N-type epitaxial structures.


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