The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 10, 2025

Filed:

May. 28, 2024
Applicant:

Globalfoundries U.s. Inc., Malta, NY (US);

Inventors:

Dominik Martin Kleimaier, Dresden, DE;

Ruchil Kumar Jain, Dresden, DE;

Jan Höntschel, Dresden, DE;

Peter Javorka, Dresden, DE;

Steven Langdon, Dresden, DE;

Felix Holzmüller, Dresden, DE;

Assignee:

GlobalFoundries U.S. Inc., Malta, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 64/27 (2025.01); H01L 21/762 (2006.01); H10D 30/60 (2025.01); H10D 86/00 (2025.01);
U.S. Cl.
CPC ...
H10D 64/514 (2025.01); H01L 21/76267 (2013.01); H10D 30/603 (2025.01); H10D 86/201 (2025.01);
Abstract

Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure comprises a silicon-on-insulator substrate including a semiconductor substrate, a dielectric layer on the semiconductor substrate, and a semiconductor layer on the dielectric layer. The structure further comprises a gate electrode on the semiconductor layer. The gate electrode comprises a single-crystal semiconductor material. The structure further comprises a spacer structure including a first portion that overlaps with a side surface of the dielectric layer and a second portion that overlaps with a portion of the semiconductor substrate adjacent to the side surface of the dielectric layer.


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