The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 10, 2025

Filed:

Jun. 07, 2024
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Sheng-Yao Huang, Kaohsiung, TW;

Yu-Ruei Chen, New Taipei, TW;

Zen-Jay Tsai, Tainan, TW;

Yu-Hsiang Lin, New Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/65 (2025.01); H01L 21/265 (2006.01); H01L 21/28 (2025.01); H10D 30/01 (2025.01); H10D 30/60 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 64/27 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01);
U.S. Cl.
CPC ...
H10D 30/65 (2025.01); H01L 21/26533 (2013.01); H01L 21/2822 (2013.01); H10D 30/0281 (2025.01); H10D 62/116 (2025.01); H01L 21/28211 (2013.01);
Abstract

A semiconductor device includes a substrate, a buried oxide layer in the substrate and near a surface of the substrate, a gate dielectric layer on the substrate and covering the buried oxide layer, a gate structure disposed on the gate dielectric layer and overlapping the buried oxide layer, a source region and a drift region in the substrate and respectively at two sides of the gate structure, wherein the drift region partially covers a lower edge of the buried oxide layer and exposes a side edge of the buried oxide layer, and a drain region in the drift region.


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