The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 03, 2025

Filed:

Feb. 14, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Dian-Sheg Yu, Hsinchu, TW;

Ren-Fen Tsui, Hsinchu, TW;

Jhon-Jhy Liaw, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/03 (2025.01); H01L 21/28 (2025.01); H01L 21/3105 (2006.01); H10B 10/00 (2023.01); H10D 30/69 (2025.01); H10D 64/01 (2025.01); H10D 64/27 (2025.01); H10D 84/01 (2025.01); H10D 84/85 (2025.01); H10D 89/10 (2025.01);
U.S. Cl.
CPC ...
H10D 84/038 (2025.01); H01L 21/28114 (2013.01); H01L 21/3105 (2013.01); H10B 10/12 (2023.02); H10D 30/792 (2025.01); H10D 64/017 (2025.01); H10D 64/518 (2025.01); H10D 84/0151 (2025.01); H10D 84/0158 (2025.01); H10D 84/0193 (2025.01); H10D 84/853 (2025.01); H10D 30/797 (2025.01); H10D 84/0135 (2025.01); H10D 84/017 (2025.01); H10D 84/0172 (2025.01); H10D 84/0188 (2025.01); H10D 89/10 (2025.01);
Abstract

A semiconductor device includes first and second semiconductor fins, first, second, third and fourth gate structures, and a dielectric structure. The first semiconductor fin and the second semiconductor fin are over a substrate. The first gate structure and the second gate structure respectively extend across the first semiconductor fin and the second semiconductor fin. The first gate structure has a longitudinal axis aligned with a longitudinal axis of the second gate structure. The dielectric structure interposes the first gate structure and the second gate structure. The third gate structure extends across the first and second semiconductor fins. The fourth gate structure extends across the first and second semiconductor fins. The third gate structure is between the fourth gate structure and the dielectric structure. The third gate structure has a maximal width greater than a maximal width of the fourth gate structure.


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