The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 03, 2025

Filed:

Feb. 05, 2024
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Feng-Ching Chu, Hsinchu, TW;

Wei-Yang Lee, Taipei, TW;

Yen-Ming Chen, Hsin-Chu County, TW;

Feng-Cheng Yang, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 62/10 (2025.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 21/3065 (2006.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 30/69 (2025.01); H10D 62/00 (2025.01); H10D 62/13 (2025.01);
U.S. Cl.
CPC ...
H10D 62/116 (2025.01); H01L 21/02057 (2013.01); H01L 21/02227 (2013.01); H01L 21/30604 (2013.01); H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10D 30/797 (2025.01); H10D 62/021 (2025.01); H10D 62/151 (2025.01); H01L 21/3065 (2013.01);
Abstract

Various examples of an integrated circuit device and a method for forming the device are disclosed herein. In an example, a method includes receiving a workpiece that includes a substrate, and a device fin extending above the substrate. The device fin includes a channel region. A portion of the device fin adjacent the channel region is etched, and the etching creates a source/drain recess and forms a dielectric barrier within the source/drain recess. The workpiece is cleaned such that a bottommost portion of the dielectric barrier remains within a bottommost portion of the source/drain recess. A source/drain feature is formed within the source/drain recess such that the bottommost portion of the dielectric barrier is disposed between the source/drain feature and a remainder of the device fin.


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