The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 03, 2025

Filed:

Aug. 09, 2023
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Shih-Wei Liang, Dajia Township, Taichung County, TW;

Hung-Yi Kuo, Taipei, TW;

Hao-Yi Tsai, Hsinchu, TW;

Ming-Hung Tseng, Toufen Township, Miaoli County, TW;

Hsien-Ming Tu, Zhubei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01F 27/28 (2006.01); H01F 17/00 (2006.01); H01F 41/04 (2006.01); H01F 41/061 (2016.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/66 (2006.01); H02J 50/12 (2016.01); H10D 1/20 (2025.01); H10D 1/68 (2025.01); H01F 41/12 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5227 (2013.01); H01F 17/0013 (2013.01); H01F 27/2804 (2013.01); H01F 41/04 (2013.01); H01F 41/061 (2016.01); H01L 23/3157 (2013.01); H01L 23/49822 (2013.01); H01L 23/5223 (2013.01); H01L 23/5226 (2013.01); H01L 23/528 (2013.01); H01L 23/66 (2013.01); H02J 50/12 (2016.02); H10D 1/20 (2025.01); H10D 1/68 (2025.01); H01F 2017/0073 (2013.01); H01F 2027/2809 (2013.01); H01F 41/122 (2013.01); H01L 23/5389 (2013.01); H01L 24/20 (2013.01); H01L 2223/6655 (2013.01); H01L 2223/6672 (2013.01); H01L 2223/6677 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/24195 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73267 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19042 (2013.01); H01L 2924/19105 (2013.01);
Abstract

A method of making a semiconductor device, includes: forming a first molding layer on a substrate; forming a first plurality of vias in the first molding layer; forming a first conductive line over the first molding layer, wherein the first conductive line is laterally disposed over the first molding layer and a first end of the conductive line aligns with and is electrically coupled to a first via of the first plurality of vias; forming a second molding layer above the first molding layer; and forming a second plurality of vias in the second molding layer, wherein a second via of the second plurality of vias aligns with and is electrically coupled to a second end of the conductive line, and wherein the second plurality of vias, the conductive line, and the first plurality of vias are electrically coupled to one another.


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