The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 03, 2025
Filed:
Jul. 25, 2024
Adeia Semiconductor Bonding Technologies Inc., San Jose, CA (US);
Ron Zhang, Sunnyvale, CA (US);
Gaius Gillman Fountain, Jr., Youngsville, NC (US);
Belgacem Haba, Saratoga, CA (US);
Kyong-Mo Bang, Fremont, CA (US);
Laura Wills Mirkarimi, Sunol, CA (US);
Suhail Jaan Sadiq, Dublin, CA (US);
Adeia Semiconductor Bonding Technologies Inc., San Jose, CA (US);
Abstract
Embodiments herein provide for fluidic cooling assemblies embedded within a device package and related manufacturing methods. In one embodiment, the integrated cooling assembly includes a semiconductor device and a cold plate attached to the semiconductor device. The cold plate has a perimeter sidewall, a top portion and pairs of opposing cavity sidewalls. The perimeter sidewall extends downwardly from the top portion to a backside of the semiconductor device to define a perimeter of the cold plate. Each pair of opposing cavity sidewalls extends downwardly from the top portion towards the backside of the semiconductor device to define a coolant chamber volume therebetween. A distance between each pair of opposing cavity sidewalls in a direction parallel with the backside of the semiconductor device defines a width of a corresponding coolant chamber volume and a spacing between adjacent coolant chamber volumes, wherein the ratio of width to spacing is about 1:1.