The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 03, 2025

Filed:

Mar. 30, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Narasimha Lanka, Dublin, CA (US);

Swadesh Choudhary, Mountain View, CA (US);

Debendra Das Sharma, Saratoga, CA (US);

Lakshmipriya Seshan, Sunnyvale, CA (US);

Zuoguo Wu, San Jose, CA (US);

Gerald Pasdast, San Jose, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/42 (2006.01); G06F 13/40 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4273 (2013.01); G06F 13/405 (2013.01); H01L 23/5383 (2013.01); H01L 25/0655 (2013.01); G06F 2213/0024 (2013.01); G06F 2213/0026 (2013.01); H01L 24/16 (2013.01); H01L 2224/16225 (2013.01);
Abstract

In one embodiment, an apparatus includes: a die-to-die adapter to communicate with protocol layer circuitry and physical layer circuitry; and the physical layer circuitry coupled to the die-to-die adapter, where the physical layer circuitry is to receive and output first information to a second die via an interconnect. The physical layer circuitry may include: a first sideband data receiver to couple to a first sideband data lane and a first sideband clock receiver to couple to a first sideband clock lane; and a second sideband data receiver to couple to a second sideband data lane and a second sideband clock receiver to couple to a second sideband clock lane. The physical layer circuitry may assign a functional sideband comprising: one of the first or second sideband data lanes; and one of the first or second sideband clock lanes. Other embodiments are described and claimed.


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