The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 27, 2025
Filed:
Sep. 18, 2020
Intel Corporation, Santa Clara, CA (US);
Sairam Subramanian, Portland, OR (US);
Walid M. Hafez, Portland, OR (US);
Hsu-Yu Chang, Hillsboro, OR (US);
Chia-Hong Jan, Portland, OR (US);
Tanuj Trivedi, Hillsboro, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Adjacent gate-all-around integrated circuit structures having non-merged epitaxial source or drain regions, and methods of fabricating adjacent gate-all-around integrated circuit structures having non-merged epitaxial source or drain regions, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate. One or more gate stacks is over the first and second vertical arrangements of nanowires. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. An intervening dielectric structure is between adjacent ones of the first epitaxial source or drain structures and between adjacent ones of the second epitaxial source or drain structures.