The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 27, 2025

Filed:

Jul. 31, 2023
Applicants:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Tsmc China Company Limited, Shanghai, CN;

Inventors:

Feng Han, Shanghai, CN;

Lei Shi, Shanghai, CN;

Hung-Chih Tsai, Kaohsiung County, TW;

Liang-Yu Su, Yunlin County, TW;

Hang Fan, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/94 (2006.01); H01L 29/76 (2006.01); H10D 30/01 (2025.01); H10D 30/65 (2025.01); H10D 62/10 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H10D 30/0281 (2025.01); H10D 30/65 (2025.01); H10D 62/115 (2025.01); H10D 84/0128 (2025.01); H10D 84/038 (2025.01);
Abstract

A semiconductor device includes a doped region of a first conductivity type in a substrate, a source/drain region of the first conductivity in the doped region, and a gate structure overlapping a portion of the doped region. The semiconductor device further comprises a multi-layer spacer over a first sidewall of the gate structure. The multi-layer spacer comprises a first spacer layer, a second spacer layer over the first spacer layer, and a third spacer layer over the second spacer layer. The first spacer layer and the second spacer layer are in contact with the first sidewall of the gate structure.


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