The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 27, 2025

Filed:

Nov. 23, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Mrunal Abhijith Khaderbad, Hsinchu, TW;

Wei-Yen Woon, Hsinchu, TW;

Cheng-Ming Lin, Kaohsiung, TW;

Han-Yu Lin, Hsinchu, TW;

Szu-Hua Chen, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/67 (2006.01); H01L 21/285 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/45 (2006.01);
U.S. Cl.
CPC ...
H01L 29/401 (2013.01); H01L 21/28518 (2013.01); H01L 21/28525 (2013.01); H01L 21/28568 (2013.01); H01L 29/41733 (2013.01); H01L 29/41791 (2013.01); H01L 29/42392 (2013.01); H01L 29/456 (2013.01);
Abstract

The present disclosure describes a semiconductor device and a method for forming the semiconductor device. The method includes forming a fin structure on a substrate, forming a gate structure on the fin structure, and forming a source/drain (S/D) region on the fin structure not covered by the gate structure. The method further includes forming a contact structure on the S/D region. Forming the contact structure includes forming a transition metal chalcogenide (TMC) layer on the S/D region, and forming a contact plug on the TMC layer.


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