The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 27, 2025

Filed:

Jan. 14, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Jiewen Yao, Shanghai, CN;

David Harriman, Portland, OR (US);

Xiaoyu Ruan, Folsom, CA (US);

Mahesh Natu, Folsom, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/42 (2006.01); G06F 13/40 (2006.01); G06F 21/57 (2013.01); G06F 21/85 (2013.01);
U.S. Cl.
CPC ...
G06F 21/572 (2013.01); G06F 13/4022 (2013.01); G06F 13/4221 (2013.01); G06F 21/577 (2013.01); G06F 21/85 (2013.01);
Abstract

Various embodiments provide apparatuses, systems, and methods for establishing, by a data object exchange (DOE entity) of a peripheral component interconnect express (PCIe) device, a first session for communication between a first host entity of a host device and a first PCIe entity of the PCIe device, and a second session for communication between a second host entity of the host device and a second PCIe entity of the PCIe device. The first session may have a first security policy and be a session of a first connection between the PCIe device and the host device. The second session may have a second security policy and be a session of a second connection between the PCIe device and the host device. Other embodiments may be described and claimed.


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