The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 20, 2025
Filed:
Jun. 08, 2021
Intel Corporation, Santa Clara, CA (US);
Wilfred Gomes, Portland, OR (US);
Abhishek A. Sharma, Hillsboro, OR (US);
Van H. Le, Beaverton, OR (US);
Hui Jae Yoo, Hillsboro, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
IC devices with stacked backend memory with resistive switching devices are disclosed. An example IC device includes a support structure, a frontend layer with a plurality of frontend devices, and a backend layer with a plurality of resistive switching devices, the resistive switching devices being, e.g., part of memory cells of stacked backend memory. For example, the backend layer may implement stacked arrays of 1T-1RSD memory cells, with resistive switching devices coupled to some S/D regions of access transistors of the memory cells. Such memory cells may be used to implement stacked eMRAM or eRRAM, with access transistors being TFTs. Stacked TFT-based eMRAM or eRRAM as described herein may help increase density of MRAM or RRAM cells, hide the peripheral circuits that control the memory operation below the memory arrays, and address the scaling challenge of some conventional memory technologies.