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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12308253 B1

PDFFull Text
Date of Patent:
May. 20, 2025

Filed:

Jul. 12, 2022

Molded product for semiconductor strip and method of manufacturing semiconductor package

Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Seunghwan Kim, Sejong-si, KR;

Kyonghwan Koh, Asan-si, KR;

Jungjoo Kim, Hwaseong-si, KR;

Jongwan Kim, Cheonan-si, KR;

Junwoo Park, Asan-si, KR;

Hyunggil Baek, Suwon-si, KR;

Yongkwan Lee, Hwaseong-si, KR;

Dongju Jang, Asan-si, KR;

Taejun Jeon, Asan-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Gyeonggi-do, KR;

Attorney:

HARNESS, DICKEY & PIERCE, P.L.C.

Primary Examiner:

Nicholas J Tobergte

Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 25/10 (2006.01); H01L 21/48 (2006.01); H01L 21/67 (2006.01);
U.S. Cl.
CPC ...
H01L 21/566 (2013.01); H01L 21/561 (2013.01); H01L 21/563 (2013.01); H01L 23/3142 (2013.01); H01L 23/49816 (2013.01); H01L 23/49833 (2013.01); H01L 23/49838 (2013.01); H01L 23/49894 (2013.01); H01L 24/96 (2013.01); H01L 24/97 (2013.01); H01L 25/105 (2013.01); H01L 21/4857 (2013.01); H01L 21/67126 (2013.01); H01L 23/49822 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 2224/16237 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/9511 (2013.01); H01L 2225/1023 (2013.01); H01L 2225/1041 (2013.01); H01L 2225/107 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/1438 (2013.01); H01L 2924/1811 (2013.01); H01L 2924/1815 (2013.01); H01L 2924/182 (2013.01); H01L 2924/183 (2013.01); H01L 2924/186 (2013.01);
Abstract

A method of manufacturing a semiconductor package may include providing a substrate having first and second cutting regions respectively provided along first and second side portions opposite to each other and a mounting region between the first and second cutting regions is provided, disposing at least one semiconductor chip on the mounting region, forming a molding member on the substrate, and removing a dummy curl portion and at least portions of dummy runner portions from the molding member. The molding member may include a sealing portion, the dummy curl portion provided outside the second side portion of the substrate, and the plurality of dummy runner portions on the second cutting region to connect the sealing portion and the dummy curl portion. The substrate may include adhesion reducing pads in the second cutting region, which may contact the dummy runner portions respectively.

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