The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 13, 2025

Filed:

Mar. 05, 2024
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Hsin-Wen Su, Yunlin County, TW;

Yu-Kuan Lin, Taipei, TW;

Shih-Hao Lin, Hsinchu, TW;

Lien-Jung Hung, Taipei, TW;

Ping-Wei Wang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/306 (2006.01); H10B 20/00 (2023.01); H10B 20/25 (2023.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6757 (2025.01); H01L 21/02532 (2013.01); H01L 21/02603 (2013.01); H01L 21/30604 (2013.01); H10B 20/00 (2023.02); H10B 20/25 (2023.02); H10D 30/031 (2025.01); H10D 30/673 (2025.01); H10D 30/6735 (2025.01); H10D 30/6739 (2025.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01);
Abstract

A memory device includes a substrate, a first transistor and a second transistor, a first word line, a second word line, and a bit line. The first transistor and the second transistor are over the substrate and are electrically connected to each other, in which each of the first and second transistors includes first semiconductor layers and second semiconductor layers, a gate structure, and source/drain structures, in which the first semiconductor layers are in contact with the second semiconductor layers, and a width of the first semiconductor layers is narrower than a width of the second semiconductor layers. The first word line is electrically connected to the gate structure of the first transistor. The second word line is electrically connected to the gate structure of the second transistor. The bit line is electrically connected to a first one of the source/drain structures of the first transistor.


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