The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 13, 2025

Filed:

Nov. 17, 2022
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Mukta Ghate Farooq, Hopewell Junction, NY (US);

Qianwen Chen, Chappaqua, NY (US);

Shahid Butt, Ossining, NY (US);

Eric Perfecto, Poughkeepsie, NY (US);

Michael P. Belyansky, Halfmoon, NY (US);

Katsuyuki Sakuma, Fishkill, NY (US);

John Knickerbocker, Monroe, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/535 (2006.01); B32B 43/00 (2006.01); H01L 21/683 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 23/535 (2013.01); H01L 21/6835 (2013.01); H01L 21/6836 (2013.01); H01L 23/5225 (2013.01); H01L 23/5283 (2013.01); B32B 43/006 (2013.01); H01L 2221/68318 (2013.01); H01L 2221/68327 (2013.01); H01L 2221/6835 (2013.01); H01L 2221/68354 (2013.01); H01L 2221/68368 (2013.01);
Abstract

A stack structure that includes: a device wafer, a handler wafer, and a bonding structure disposed between the device wafer and the handler wafer, wherein one or both of the device wafer and the handler wafer have a release layer that is configured to be substantially or completely vaporized by infrared ablation when exposed to an infrared laser energy. The device wafer includes at least two consecutive layers adjacent the bonding structure that together include a plurality of fill portions that substantially or completely disable entry of the infrared laser energy into a plurality of layers of the device wafer below the two consecutive layers adjacent the bonding structure.


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