The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 06, 2025

Filed:

Aug. 09, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chen-Ping Chen, Toucheng Township, TW;

Kuei-Yu Kao, Hsinchu, TW;

Shih-Yao Lin, New Taipei, TW;

Chih-Han Lin, Hsinchu, TW;

Ming-Ching Chang, Hsinchu, TW;

Chao-Cheng Chen, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2005.12); H01L 21/8234 (2005.12); H01L 21/8238 (2005.12); H01L 29/78 (2005.12);
U.S. Cl.
CPC ...
H01L 29/66795 (2012.12); H01L 21/823431 (2012.12); H01L 21/823468 (2012.12); H01L 21/823821 (2012.12); H01L 21/823864 (2012.12); H01L 29/66545 (2012.12); H01L 29/6656 (2012.12); H01L 29/7851 (2012.12); H01L 2029/7858 (2012.12);
Abstract

A device includes a fin protruding from a semiconductor substrate; a gate stack over and along a sidewall of the fin; a gate spacer along a sidewall of the gate stack and along the sidewall of the fin; an epitaxial source/drain region in the fin and adjacent the gate spacer; and a corner spacer between the gate stack and the gate spacer, wherein the corner spacer extends along the sidewall of the fin, wherein a first region between the gate stack and the sidewall of the fin is free of the corner spacer, wherein a second region between the gate stack and the gate spacer is free of the corner spacer.


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