The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 06, 2025

Filed:

Sep. 06, 2024
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Thomas Aichinger, Faak am See, AT;

Dethard Peters, Höchstadt, DE;

Michael Hell, Erlangen, DE;

Andreas Hürner, Heroldsberg, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/16 (2005.12); H01L 29/43 (2005.12); H01L 29/51 (2005.12); H01L 29/78 (2005.12);
U.S. Cl.
CPC ...
H01L 29/1608 (2012.12); H01L 29/435 (2012.12); H01L 29/518 (2012.12); H01L 29/7813 (2012.12);
Abstract

A power semiconductor device is proposed. The vertical power semiconductor device includes a silicon carbide (SiC) semiconductor body having a first surface and a second surface opposite to the first surface. The SiC semiconductor body includes a transistor cell area comprising gate structures, a gate pad area, and an interconnection area electrically coupling a gate electrode of the gate structures and a gate pad of the gate pad area via a gate interconnection. The vertical power semiconductor device further includes a source or emitter electrode. The vertical power semiconductor device further includes a first interlayer dielectric comprising a first interface to the source or emitter electrode and a second interface to at least one of the gate electrode, or the gate interconnection, or the gate pad, and wherein a conduction band offset at the first interface ranges from 1 eV to 2.5 eV.


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