The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 06, 2025

Filed:

Dec. 07, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Yung-Lung Lin, Taichung, TW;

Cheng-Hsien Chou, Tainan, TW;

Cheng-Yuan Tsai, Chu-Pei, TW;

Kuo-Ming Wu, Zhubei, TW;

Hau-Yi Hsiao, Chiayi, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/822 (2005.12); H01L 21/304 (2005.12); H01L 27/06 (2005.12); H01L 29/06 (2005.12);
U.S. Cl.
CPC ...
H01L 21/8221 (2012.12); H01L 21/304 (2012.12); H01L 27/0688 (2012.12); H01L 29/0657 (2012.12);
Abstract

The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first substrate having a first horizontally extending surface and a second horizontally extending surface above the first horizontally extending surface as viewed in a cross-sectional view. The first horizontally extending surface continuously wraps around an outermost perimeter of the second horizontally extending surface in a closed loop as viewed in a plan-view. A second substrate is disposed over the first substrate and includes a third horizontally extending surface above the second horizontally extending surface as viewed in the cross-sectional view. The second horizontally extending surface continuously wraps around an outermost perimeter of the third horizontally extending surface in a closed loop as viewed in the plan-view.


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