The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 29, 2025

Filed:

Mar. 25, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chung-Wei Hsu, Baoshan Township, TW;

Kuo-Cheng Chiang, Zhubei, TW;

Mao-Lin Huang, Hsinchu, TW;

Lung-Kun Chu, New Taipei, TW;

Jia-Ni Yu, New Taipei, TW;

Chun-Fu Lu, Hsinchu, TW;

Chih-Hao Wang, Baoshan Township, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/324 (2005.12); H01L 21/8234 (2005.12); H01L 29/06 (2005.12); H01L 29/423 (2005.12); H01L 29/66 (2005.12); H01L 29/786 (2005.12);
U.S. Cl.
CPC ...
H01L 21/324 (2012.12); H01L 21/823412 (2012.12); H01L 29/0665 (2012.12); H01L 29/42392 (2012.12); H01L 29/66742 (2012.12); H01L 29/78618 (2012.12); H01L 29/78696 (2012.12);
Abstract

A method of forming a semiconductor device includes forming a first dielectric layer over a first channel region in a first region and over a second channel region in a second region; introducing a first dipole element into the first dielectric layer in the first region to form a first dipole-containing gate dielectric layer in the first region; forming a second dielectric layer over the first dipole-containing gate dielectric layer; introducing fluorine into the second dielectric layer to form a first fluorine-containing gate dielectric layer over the first dipole-containing gate dielectric layer; and forming a gate electrode over the first fluorine-containing gate dielectric layer.


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