The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2025

Filed:

Mar. 16, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Sung-Hsin Yang, Tainan, TW;

Ru-Shang Hsiao, Jhubei, TW;

Ching-Hwanq Su, Tainan, TW;

Chen-Bin Lin, Tainan, TW;

Wen-Hsin Chan, Zhubei, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2005.12); H01L 21/306 (2005.12); H01L 21/308 (2005.12); H01L 21/8238 (2005.12);
U.S. Cl.
CPC ...
H01L 27/0922 (2012.12); H01L 21/30604 (2012.12); H01L 21/308 (2012.12); H01L 21/823807 (2012.12); H01L 21/823821 (2012.12); H01L 21/823878 (2012.12); H01L 27/0924 (2012.12);
Abstract

A structure includes a bulk semiconductor substrate, a first plurality of dielectric isolation regions over the bulk semiconductor substrate, a plurality of semiconductor fins protruding higher than the first plurality of dielectric isolation regions, a first gate stack on top surfaces and sidewalls of the plurality of semiconductor fins, a second plurality of dielectric isolation regions over the bulk semiconductor substrate, a mesa structure in the second plurality of dielectric isolation regions, and a second gate stack over the mesa structure. Top surfaces of the first gate stack and the second gate stack are coplanar with each other.


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