The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2025

Filed:

Mar. 16, 2022
Applicant:

Yangtze Memory Technologies Co., Ltd., Hubei, CN;

Inventors:

Di Wang, Hubei, CN;

Zhong Zhang, Hubei, CN;

Wenxi Zhou, Hubei, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/535 (2005.12); H01L 21/768 (2005.12); H01L 23/00 (2005.12); H01L 25/00 (2005.12); H01L 25/065 (2022.12); H01L 25/18 (2022.12);
U.S. Cl.
CPC ...
H01L 23/535 (2012.12); H01L 21/76805 (2012.12); H01L 21/76895 (2012.12); H01L 24/08 (2012.12); H01L 24/80 (2012.12); H01L 25/0657 (2012.12); H01L 25/18 (2012.12); H01L 25/50 (2012.12); H01L 2224/08145 (2012.12); H01L 2224/80895 (2012.12); H01L 2224/80896 (2012.12); H01L 2924/1431 (2012.12); H01L 2924/14511 (2012.12);
Abstract

The present disclosure describes a three-dimensional (3D) memory device includes first and second memory arrays disposed on a semiconductor layer. The 3D memory device can also include a staircase structure disposed between the first and second memory arrays. The staircase structure includes first and second staircase regions. The first staircase region includes a first staircase structure that contains a first plurality of stairs descending in a first direction. The second staircase region includes a second staircase structure that contains a second plurality of stairs descending in a second direction. The 3D memory device can also include a contact region disposed between the first and second staircase regions. The contact region includes a plurality of contacts the extending through an insulating layer and into the semiconductor layer.


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