The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2025

Filed:

Mar. 20, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Ming-Che Lee, Tainan, TW;

Kuo-Ming Wu, Zhubei, TW;

Sheng-Chau Chen, Tainan, TW;

Hau-Yi Hsiao, Chiayi, TW;

Guanyu Luo, Chiayi County, TW;

Ping-Tzu Chen, Tainan, TW;

Cheng-Yuan Tsai, Chu-Pei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/18 (2005.12); H01L 21/3105 (2005.12); H01L 23/00 (2005.12); H01L 23/522 (2005.12); H01L 25/00 (2005.12); H01L 25/065 (2022.12);
U.S. Cl.
CPC ...
H01L 23/18 (2012.12); H01L 21/31051 (2012.12); H01L 23/5226 (2012.12); H01L 23/562 (2012.12); H01L 24/80 (2012.12); H01L 25/50 (2012.12); H01L 24/08 (2012.12); H01L 25/0657 (2012.12); H01L 2224/08146 (2012.12); H01L 2224/80001 (2012.12); H01L 2924/37001 (2012.12);
Abstract

The present disclosure relates to a semiconductor wafer structure including a semiconductor substrate and a plurality of semiconductor devices disposed along the semiconductor substrate. A dielectric stack including a plurality of dielectric layers is arranged over the semiconductor substrate. A conductive interconnect structure is within the dielectric stack. A seal ring layer is over the dielectric stack and laterally surrounds the dielectric stack along a first sidewall of the dielectric stack. The seal ring layer includes a first protrusion that extends into a first trench in the semiconductor substrate.


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