The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 08, 2025

Filed:

Jun. 05, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Haohua Zhou, Fremont, CA (US);

Tze-Chiang Huang, Saratoga, CA (US);

Mei Hsu Wong, Saratoga, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 30/30 (2020.01); G06F 30/367 (2020.01); G06F 30/39 (2020.01); H01L 23/50 (2006.01); H01L 23/528 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
G06F 30/30 (2020.01); G06F 30/367 (2020.01); G06F 30/39 (2020.01); H01L 23/50 (2013.01); H01L 23/5286 (2013.01); H01L 23/5384 (2013.01);
Abstract

A method includes: extracting a first current profile model corresponding to a System on Chip (SOC) at a first design stage of the SOC; determining that a first design data of an Integrated Voltage Regulator (IVR) and the SOC pass a first co-simulation based on the extracted first current profile model; extracting a second current profile model corresponding to the SOC at a second design stage of the SOC, the second design stage being subsequent to the first design stage; refining the first design data of the IVR to generate a second design data of the IVR; determining that the second design data of the IVR and the SOC pass a second co-simulation based on the extracted second current profile model.


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