The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 01, 2025

Filed:

Dec. 27, 2021
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Ruilong Xie, Niskayuna, NY (US);

Kisik Choi, Watervliet, NY (US);

Somnath Ghosh, Clifton Park, NY (US);

Sagarika Mukesh, Albany, NY (US);

Albert Chu, Nashua, NH (US);

Albert M. Young, Fishkill, NY (US);

Balasubramanian S. Pranatharthiharan, Santa Clara, CA (US);

Huiming Bu, Glenmont, NY (US);

Kai Zhao, Albany, NY (US);

John Christopher Arnold, North Chatham, NY (US);

Brent A. Anderson, Jericho, VT (US);

Dechao Guo, Niskayuna, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 89/10 (2025.01); H01L 21/762 (2006.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01);
U.S. Cl.
CPC ...
H10D 89/10 (2025.01); H01L 21/76229 (2013.01); H10D 30/6735 (2025.01); H10D 62/121 (2025.01); H10D 84/0149 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01); H10D 86/471 (2025.01); H10D 86/60 (2025.01);
Abstract

A device comprises a first interconnect structure, a second interconnect structure, a first cell comprising a first transistor, a second cell comprising a second transistor, a first contact connecting a source/drain element of the first transistor to the first interconnect structure, and second contact connecting a source/drain element of the second transistor to the second interconnect structure. The first cell is disposed adjacent to the second cell with the first transistor disposed adjacent to the second transistor. The first and second cells are disposed between the first and second interconnect structures.


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